十博DDR5提供高达2倍的内存带宽1 与DDR4相比, which is required to feed the accelerating growth of CPU cores in the modern data center.


Micron DDR5: Offering More Than 2X the Effective Bandwidth

DDR5 will offer up to 2x the effective bandwidth when compared to its predecessor DDR4, 帮助缓解每个核心的带宽危机.

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Micron DDR5: Next-Generation Memory Transforming Data Into Insight

Watch how Micron DDR5 addresses the memory bandwidth per CPU challenge and transforms available data into insight.

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Micron DDR5 memory delivers up to 2x the effective memory bandwidth 与DDR4相比, which is required to feed the continued growth of CPU cores in the data center and the next generation of client systems.


Micron DDR5 memory is designed to improve reliability across the data center with features such as on-die error correction code (ODECC) and bounded faults. ODECC corrects single bit errors and detects multi-bit errors.


Micron DDR5 memory sports 16Gb and 24Gb densities today, 未来芯片密度可达64Gb, 内存密度是DDR4的4倍. Scaling capacity and performance will not be a bottleneck for productivity with Micron DDR5 memory.



The DDR5 Technical Enablement Program (TEP) is a program that offers a path into Micron to gain early access to technical information and support, electrical and thermal models as well as DDR5 products to aid in the design, development and bring-up of next-generation computing platforms.

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  • 16Gb
Range: 16Gb
  • Width
    x8, x16
  • Voltage
  • Package
  • Clock Rate
    2400 MHz
  • Op. Temp.
    0C to +95C


Micron DDR5 is game-changing memory for the data center, 可在4800 MT/s的各种密度.



Micron DDR5 Delivers Next-Gen Performance and Reliability for the 4th Gen Intel®️ Xeon®️ 可扩展处理器系列

Micron DDR5 improves workloads across the data center today while enabling future infrastructure growth.

Micron DDR5 Memory Now Available for 4th Gen AMD EPYC Processors

The combination scales up to 2x the performance for select HPC memory-bound workloads.


Listen to a podcast discussing the impact of Micron DDR5 memory and the promise it holds for data center and cloud workloads.

Boost HPC Workloads With Micron DDR5 and 4th Gen AMD EPYC Processors 

Micron DDR5 with 4th Gen AMD EPYC processors runs HPC workloads two times faster than systems using DDR4 and AMD “Zen 3” architecture, all while allowing double the memory bandwidth per core over these previous-generation systems.


我们所做的就是与战略伙伴合作. Our relationships with preferred partners and key enablers are our top priority. 通过这些关系, we're building ecosystems that promote connections and co-development efforts that lead to better solutions for our customers.


DDR5是DRAM的下一个进化, bringing a robust list of new features geared to increase reliability, availability, and serviceability (RAS); reduce power; and dramatically improve performance. Some of the key feature differences between DDR4 and DDR5 are as follows:

特性/选项 DDR4 DDR5 DDR5优势
 Data rates  1600 - 3200 MT / s  4800 - 8800 MT / s  提高性能和带宽
 VDD/VDDQ/VPP   1.2/1.2/2.5   1.1/1.1/1.8   Lowers power
 设备密度    2Gb-16Gb    16Gb-64Gb    支持更大的单片设备 
 Prefetch    8n   16n    保持内部核心时钟低
 DQ接收机均衡   CTLE  DFE  改进接收到的DQ数据的打开
 占空比调整(DCA)   None   DQS and DQ  改进传输的DQ/DQS引脚的信令
 None   DQS间隔振荡器   增加对环境变化的健壮性 
 On-die ECC  None  128b+8b秒,错误检查和清除   增强片上RAS
 CRC   Write   Read/Write    通过保护读数据加强系统RAS 
 银行集团/银行   4个BG x4家银行(x4/x8)
 2个BG x 4家银行(x16)
 8 BG x4银行(16-64Gb x4/x8)
 4 BG x 4银行(16-64Gb x16) 
 命令/地址接口   Odt, cke, act, ras,


 ODT  Dq dqs dm / dbi   DQ, DQS, DM, CA总线    提高信号完整性,降低BOM成本 
 Burst length  BL8(和BC4)   BL16 
 (及BC8 OTF) 
 Allows 64B cache line fetch with only 1 DIMM subchannel. 
 MIR(“镜像”别针)   None  Yes  改进DIMM信令
 总线反演   数据总线反转(DBI)  命令/地址反转(CAI)   Reduces VDDQ noise
 CA培训,CS培训   None   CA培训,CS培训   改进CA和CS引脚的时间裕度  
 编写水平培训模式   Yes  Improved  补偿不匹配的DQ-DQS路径
 阅读培训模式   可能与MPR  串行专用MRs
 模式寄存器  7 x 17 bits  最多256 x 8位
 预先充电命令   所有银行和每家银行  所有银行,每家银行,同一家银行   PREsb可以在每个BG中预充一个银行
 刷新命令   All bank   所有银行和同一家银行  REFsb可以在每个BG中刷新一个银行
 环回模式  None   Yes  支持DQ和DQS信令测试